1. Field of the Invention
The present invention relates to the structure analysis of the design data of the HDL.
2. Description of the Related Art
In generating the conventional LSI, a developer normally generates an RTL (register transfer level) using the HDL (hardware description language), generates an analyzing DB, and composing a logic about the analyzing DB, thereby generating an LSI. The structure analysis in the above-mentioned generating process consumes a lot of computer resources. Therefore, it is possibly necessary to take measures by dividing a target LSI and composing a logic, etc.
When an error is detected, the HDL designed product is amended and the structure analysis is performed again. Therefore, a long time and a number of process steps are required. Recently, with a larger scale LSI, the restrictions on the computer resources (memory, etc.) used in the structure analysis have caused the necessity to take measures by dividing an HDL designed product in performing the structure analysis.
In Japanese Published Patent Application No. 2003-216672, an asynchronous path analysis can be easily performed and the time required to compose a logic can be shortened in the semiconductor circuit design of an LSI. In Japanese Published Patent Application No. 2003-216672, the circuit data of the RTL description is read, an asynchronous path in the circuit is detected based on the circuit data of the RTL description, an array is extracted from the detected asynchronous path, the arrays of asynchronous paths are collectively displayed, an asynchronous path is selected as a false path, an asynchronous path corresponding to a false path is deleted from the target of the optimization of a circuit, and a circuit at a gate level is generated from the circuit data of the RTL description.
In Japanese Published Patent Application No. Hei 09-311882, the portion of the RTL HDL description to be logically verified is extracted and optimized, and the speed of the simulating process can be increased. In Japanese Published Patent Application No. Hei 09-311882, the RTL HDL description is analyzed and the logical converting process and the register generating process are performed, thereby converting the RTL HDL description to a network list. Then, an observation point of the logical circuit and an input point to be fixed as a constant in the input points are specified. Then, reference and tracing of a propagation relation are performed to downsize the circuit. Furthermore, residual registers that are not intended for observation are moved and integrated for further optimization. Afterwards, a redundant logic is optimized, and then the optimized network list is converted attain to the RTL HDL description, and a simulation pattern is amended depending on the optimization.
FIG. 1 shows an analyzing procedure of the conventional analyzing process. In the analyzing process, a master DB 201 is first generated from an HDL design document 200. Then, an analyzing process 203 is performed on the structured master DB 201, thereby obtaining analysis result data 204.
In the analyzing process 203, an element of a root is obtained from the master DB (1). It is described whether or not the analysis is required. If an analysis is required, the analysis process is performed, and a result is stored (2). An element of a child is obtained (An element of a parent is stored) (3). The processes (2) and (3) are repeated (4). These processes are repeated according to all elements.
However, when the above-mentioned analysis is performed in the conventional technology, the analyzing DB is very large. Therefore, it takes a long time to perform the analyzing process. Furthermore, with a lot of HDL designed data, the computer resources (memory, etc.) have been short. That is, in the conventional technology, there is no database optimized for the necessary analysis contents.
Additionally, when an error is detected, the RTL is to be amended, and it is necessary to regenerate the analyzing DB from the RTL. That is, when an error is detected, an HDL designed product is amended, and each time it is amended, the analyzing DB is restructured and an analysis is performed again. However, since the analyzing process requires a very long time, the operation cannot be efficiently performed because a common analysis system is specified for detection of an error, and a rearranging test cannot be conducted on an HDL designed product in the memory, thereby requiring repeated amendments to the design product and analyzing process.
Furthermore, there can be different composition rules depending on the logical composition tool, thereby different output results are obtained. That is, a circuit different from an analysis result can be generated.